Fidelity benchmarks for two-qubit gates in silicon

W. Huang, C. H. Yang, K. W. Chan, T. Tanttu, B. Hensen, R. C. C. Leon, M. A. Fogarty, J. C. C. Hwang, F. E. Hudson, K. M. Itoh, A. Morello, A. Laucht, A. S. Dzurak

Published 2018-05-14Version 1

Universal quantum computation will require qubit technology based on a scalable platform, together with quantum error correction protocols that place strict limits on the maximum infidelities for one- and two-qubit gate operations. While a variety of qubit systems have shown high fidelities at the one-qubit level, superconductor technologies have been the only solid-state qubits manufactured via standard lithographic techniques which have demonstrated two-qubit fidelities near the fault-tolerant threshold. Silicon-based quantum dot qubits are also amenable to large-scale manufacture and can achieve high single-qubit gate fidelities (exceeding 99.9 %) using isotopically enriched silicon. However, while two-qubit gates have been demonstrated in silicon, it has not yet been possible to rigorously assess their fidelities using randomized benchmarking, since this requires sequences of significant numbers of qubit operations ($\gtrsim 20$) to be completed with non-vanishing fidelity. Here, for qubits encoded on the electron spin states of gate-defined quantum dots, we demonstrate Bell state tomography with fidelities ranging from 85 % to 92 % and two-qubit randomized benchmarking with an average Clifford gate fidelity of 77 % and average Controlled-ROT (CROT) fidelity of 91 %. These fidelities are found to be limited by the relatively slow gate times employed here compared with the decoherence times $T_2^*$ of the qubits. Silicon qubit designs employing fast gate operations based on high Rabi frequencies, together with advanced pulsing techniques, should therefore enable significantly higher fidelities in the near future.